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73S8009R low cost versatile smart card interface simplifying system integration ? data sheet ds_80 09r_056 october 2009 rev. 1.3 ? 2009 teridian semiconductor corporation 1 description the 73S8009R is a very low - cost level shifter, single smart card (icc) interface ic. the device includes a level shifter interface between a 3.3 v (typical) logic circuitry (host microcontroller) and an iso - 7816 / emv smart card. the 73S8009R is designed to provide full electrical compliance with iso - 7816 - 3 emv4.1 (emv2000) and gsm11 - 11 specifications. in normal operating mode , for maximum designer flexibility, the host micr ocontroller is responsible for card activation and deactivation. t he 73S8009R incorporates an iso - 7816 - 3 deactivation sequencer that controls the card signals in case of fault detection and card removal. card presence and faults are reported to the host through an interrupt output . w hen the 73S8009R is ready to support a card with the selected voltage, a rdy signal informs the host it can initiate the card activation sequence. the 73S8009R supports 5v, 3v and 1.8v cards. selection is done through 2 dedicated digital inputs. level - shifters drive the card signa ls with the selected card voltage coming from an internal low drop - out (ldo) voltage regulator. th e ldo regulator is powered by a dedicated power supply input , vpc. digital circuitry is separately powered by a digital power supply , vdd. emergency card deactivation is initiated upon card extraction or any fault generated by the protection circuitry. the fault can be a card over - current, a vdd (digital power) , a vpc (regulator power), a vcc (card power output) or an over - heating fault. a chip select d igital input drives internal latches that allow the host controller to control multiple 73S8009R ics in parallel. a power down digital input also allows the host mi cr ocontroller to place the ic in a very low - power mode making the 73S8009R particularly sui table for low - power and battery - powered applications. auxiliary i/o lines are also available (so28 package only) and make the 73S8009R suitable for all kind of cards, including synchronous (memory) cards. applications ? set - top - box conditional access and p ay - per - view ? sim card readers in dect and gsm phones, gprs, wifi and voip devices ? point of sales & transaction terminals ? general purpose smart card readers advantages ? lowest cost smart card interface ic on the market ? ideal to replace discrete designs in pos terminals and set - top - boxes ? traditional step - up converter is replaced by an ldo regulator ? greatly reduced power dissipation ? fewer external components are required ? better noise performance ? very low power dissipation ? small format ( 4x4 x0.8 mm) qf n 20 package option features ? c ard interface: ? complies with iso - 7816 -3 , emv 4.0 and gsm 11 - 11 specifications ? an ldo voltage regulator provides 1.8 v / 3v / 5v to the card from an external power supply input ? provides at least 90 ma to the card ? iso - 7816 - 3 card emergency d eactivation sequencer ? protection includes 3 voltage supervisors that detect voltage drops on v cc ( card), v dd (digital) and v pc (regulator) power supplies ? over - current detection , 150 ma max. ? 2 card detection input s, 1 for each user polarity ? aux iliary i/o lines for c4 / c8 contact signals ? card clk clock frequency up to 20 mhz downloaded from: http:///
73S8009R data sheet ds_8009r_056 rev. 1. 3 2 ? system controller interface ? five signal images of the card signals (rstin, clkin, iouc, aux1uc, aux2uc) ? two inputs select card voltage ( cmdvcc % , cmdvcc # ) ? two interrupt out put s ( off , rdy) inform the system controller of card presence / faults and the interface status ? chip select input (cs) ? power down input (pwrdn) ? regulator power supply (v pc ): ? class a -b- c readers: 5v, 3v and 1.8v cards: 4.75 v to 6.0 v ? digital interface ( v dd ): 2.7 v to 3.6 v ? 6 kv esd protection on the card interface ? so28 or qfn 20 package functional diagram pin numbers reference the so28 package [pin numbers] reference the qfn 20 package figure 1 : 73S8009R block diagram smart card i / o buffers ldo regulator voltage reference control logic reset buffer clock buffer over temp r-c osc . vcc fault vpc fault 1.5 mhz vdd vpc vcc rst clk pres pres i/o aux 1 aux 2 clkin iouc aux 1 uc aux 2 uc cmdvcc 5 rstin cmdvcc 3 pwrdn rdy gnd temp fault off bias currents vref gnd cs 5 [1] 67 8 [2] 9 [3] 10 [4] 11 [5] 12 [6] 13 [7] [9] 15 16 [ 10 ] 19 [ 11 ] 20 [ 12 ] 21 [ 13 ] 22 [ 14 ] 25 [ 15 ] 26 [ 16 ] [ 17 ] 28 1 [ 18 ] 4 [ 20 ] 2423 27 downloaded from: http:///
ds_8009r_056 73S8009R data sheet rev. 1.3 3 tab le of contents 1 pinout ............................................................................................................................................. 5 2 electrical specifications ................................................................................................................ 8 2.1 absolute maximum ratings ..................................................................................................... 8 2.2 recommended operating conditions ...................................................................................... 8 2.3 smart card interface requirements ........................................................................................ 9 2.4 digital signals characteristics ............................................................................................... 11 2.5 dc characteristics ................................................................................................................ 11 2.6 voltage / temperature fault detection circuits ...................................................................... 12 3 applications information ............................................................................................................. 13 3.1 example 73S8009R schematics ........................................................................................... 13 3.2 system controller interface ................................................................................................... 14 3.3 power supply and voltage supervision ................................................................................. 14 3.4 card power supply ............................................................................................................... 14 3.5 over - temperature monitor ..................................................................................................... 15 3.6 activation and deactivation sequence ................................................................................... 15 3.7 off and fault detection ....................................................................................................... 16 3.8 power - down operation .......................................................................................................... 17 3.9 chip select ........................................................................................................................... 18 3.10 i/o circuitry and timing ......................................................................................................... 18 4 mechanical drawings .................................................................................................................. 20 4.1 20 - pin qfn ........................................................................................................................... 20 4.2 28 - pin so ............................................................................................................................. 21 5 ordering information ................................................................................................................... 22 6 related documentation ............................................................................................................... 22 7 contact information ..................................................................................................................... 22 revision history .................................................................................................................................. 23 downloaded from: http:///
73S8009R data sheet ds_8009r_056 4 rev. 1.3 figures fig ure 1: 73S8009R block diagram ......................................................................................................... 2 figure 2: 73S8009R 20 - pin qfn pinout .................................................................................................. 5 figure 3: 73S8009R 28 - pin so pinout ..................................................................................................... 5 figure 4: typical 73S8009R application schematic ............................................................................... 13 figure 5: activation sequence ............................................................................................................... 15 figure 6: deactivation sequence ........................................................................................................... 16 figure 7: off activity outside and inside a card session ..................................................................... 17 figure 8: power - down operation ........................................................................................................... 17 figure 9: cs timing definitions .............................................................................................................. 18 figure 10: i/o and i/ouc state diagram ................................................................................................ 19 figure 11: i/o to i/ouc delay timing diagram ....................................................................................... 19 figure 12: 20 - pin qfn package dimensions ......................................................................................... 20 figure 13: 28 - pin so package dimensions ........................................................................................... 21 tables table 1: 73S8009R pin definitions .......................................................................................................... 6 table 2: absolute maximum device ra tings ............................................................................................ 8 table 3: recommended operating conditions ......................................................................................... 8 table 4: dc smart card interface requirements ..................................................................................... 9 table 5: digital signals characteristics .................................................................................................. 11 table 6: dc characteristics ................................................................................................................... 11 table 7: voltage / temperature fault detection circuits ......................................................................... 12 table 8: choice of vcc pin capacitor ................................................................................................... 15 table 9: order numbers and packaging marks ...................................................................................... 22 downloaded from: http:///
ds_8009r_056 73S8009R data sheet rev. 1.3 5 1 pinout the 73S8009R is supplied as a 20 - pin qfn package and as a 2 8- pin so package . 67 8 9 5 4 3 2 1 17 18 19 20 10 11 12 13 14 15 16 cs vpc pr es pres i/o clkin of f gnd vdd rstin cm dv cc% rdy pwrdn test1 clk rst vcc teridian 73S8009R test2 i/ouc cm dv cc# figure 2 : 73S8009R 20 - pin qfn pinout (top view) cs test1 off i/ouc aux2uc rstin clkin rdy pwrdn test2 vdd gnd pres aux1 i/o aux2 vcc rst gnd pr es vpc aux1uc cm dv cc% cm dv cc# clk n/c n/c n/c 1 1817 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 19 20 2827 26 25 24 23 22 21 figure 3 : 73S8009R 28- pin so pinout downloaded from: http:///
73S8009R data sheet ds_8009r_056 6 rev. 1.3 table 1 describes the pin functions for the device. table 1 : 73S8009R pin definitions pin name pin (so28) pin (qfn 20 ) type descri ption card interface i/o 25 15 io card i/o: data signal to/from card. includes a pull - up resistor to v cc. aux1 24 na io aux1: auxiliary data signal to/from card. includes a pull - up resistor to v cc. aux2 23 na io aux2: auxiliary data signal to/from card. includes a pull - up resistor to v cc. rst 21 13 o card reset: provides reset signal to card. clk 19 11 o card clock: provides clock signal to card. the rate of this clock is determined by the external clock frequency provided on pin clkin. pres 26 16 i card presence switch: active high indicates card is present. should be tied to gnd when not used, but includes a high - impedance pull - down current source . pres 16 10 i card presence switch: active low indicates card is present. should be ti ed to vd d when not used, but i ncludes a high - impedance pull - up current source. vcc 22 14 pso card power supply C logically controlled by the sequencer, output of ldo regulator. requires an external filter capacitor to gnd. gnd 20 na gnd card ground. miscellane ous inputs and outputs clk in 11 5 i clock source for the card clock. test1 2 19 C this pin must be tied to gnd in typical applications . test 2 14 8 C this pin must be tied to gnd in typical applications . nc 3,17,18 na C non - connected pin. power supply and ground vdd 28 17 system interface supply voltage and supply voltage for internal circuitry. vpc 15 9 ldo regulator power supply source. gnd 27 12 gnd g round. microcontroller interface cs 1 18 i when cs = 1, the control and signal pins are config ured normally. when cs is set low, cmdvcc% , rstin, and cmdvcc# are latched, iouc, aux1uc, and aux2uc are set to high - impedance pull - up mode and do not pass data to or from the smart card. signals rdy and off are disabled to prevent a low output and the internal pull - up resistors are disconnected. off 4 20 o interrupt signal to the processor. active l ow , m ulti - function indicating fault conditions and card presence. o pen drain output configuration. it includes an internal 20 k pull - up to vdd. the p ull - up is disabled in pwrdn and cs=0 modes. downloaded from: http:///
ds_8009r_056 73S8009R data sheet rev. 1.3 7 pin name pin (so28) pin (qfn 20 ) type descri ption i/ouc 5 1 i/o system controller data i/o to/from the card. includes a pull - up resistor to v dd. aux1uc 6 na i/o system controller auxiliary data i/o to/from the card. includes a pull -u p resistor to v dd. aux2uc 7 na i/o system controller auxiliary data i/o to/from the card. includes a pull - up resistor to v dd. cmdvcc% cmdvcc# 8 9 2 3 i i logic low on one or both of these pins will cause the ldo to ramp the vcc supply to the smart car d and smart card interface to the value described in the following table : cm dv c c% cm dv c c# v cc output voltage 0 0 1.8 v 0 1 5.0 v 1 0 3.0 v 1 1 ldo off refer to for additional information on the cmdvcc% and cmdvcc# operation. rstin 10 4 i reset input . this signal is the reset command to the card . rdy 12 6 o signal to controller indicating the 73S8009R is ready because v cc is above the required value after cmdvcc% and/or cmdvcc# is asserted low. a 20 k pull - up resistor to v dd is provided internal ly. the p ull - up is disabled in pwrdn and cs=0 modes. pwrdn 13 7 i pwrdn=1 puts the circuit into low - power mode with all analog functions disabled. the circuit will recover from the pwrdn state in the same manner as recovery from a por event, taking appr oximately 1 ms. pwrdn assertion when either cmdvcc% or cmdvcc# is low has no effect and is ignored. there is no pull - up or pull - down provided on this pin. downloaded from: http:///
73S8009R data sheet ds_8009r_056 8 rev. 1.3 2 electrical specifications this section provides the following: ? absolute maximum ratings ? recommended operating conditions ? smart card interface requirements ? digital signals characteristi cs ? dc characteristics ? voltage / temperature fault detection circuits 2.1 absolute maximum ratings table 2 lists the maximum operating conditions for the 73S8009R . permanent device damage may occur if absolute maximum ratings are exceeded. exposure to the extremes of the absolute maxi mum rating for extended periods may affect device reliability. table 2 : abs olute maximum device ratings parameter rating supply v oltage v dd - 0.5 to 4 .0 vdc supply v oltage v pc - 0.5 to 6. 5 vdc input v oltage for d igital i nputs - 0.3 to (v dd +0.5) vdc storage t emperature - 60 c to + 150 c pin v oltage (except card interface) - 0.3 to (v dd + 0.5) vdc pin v oltage (card interface) - 0.3 to (v cc + 0. 5 ) vdc esd t olerance C card interface pins +/ - 6 kv esd t olerance C other pins +/ - 2 kv note: esd testing on smart card pins is hbm condition, 3 pulses, each polarity re ferenced to groun d. smart card pins are protected against shorts between any combination of smart card pins. 2.2 recommended operating conditions function operation should be restricted to the recommended operating conditions specified in table 3 . table 3 : recommended operating conditions parameter rating supply v oltage v dd 2.7 to 3.6 vdc supply v oltage v pc for class a -b- c reader 4. 75 to 6.0 vdc ambient o perating temperature - 40 c to +85 c downloaded from: http:///
ds_8009r_056 73S8009R data sheet rev. 1.3 9 2.3 smart card interface requirements table 4 lists the 73S8009R smart card interface requirements. table 4 : dc smart card interface requirements symbol parameter condition min nom max unit card power supp ly (v cc ) regulator general conditions: - 40 c < t < 85 c, 4.75 v < v pc < 6.0 v , 2.7 v < v dd < 6.0 v v cc card supply voltage including ripple and noise inactive mode - 0.1 C 0.1 v inactive mode i cc = 1 ma - 0.1 C 0.4 active mode; i cc < 65 ma; 5 v 4.6 5 C 5.25 active mode; i cc < 65ma; 5 v , nds condition 4.75 C 5.25 active mode; i cc < 65 ma; 3 v 2.85 C 3.15 active mode; i cc < 40 ma; 1.8 v 1.68 C 1.92 active mode; single pulse of 100 ma for 2 s; 5 v, fixed load = 25 ma 4.6 C 5.25 acti ve mode; single pulse of 100 ma for 2 s; 3 v, fixed load = 25 ma 2.7 C 3.15 active mode; current pulses of 40 nas with peak |i cc | < 200 ma, t < 400 ns; 5 v 4.6 C 5.25 active mode; current pulses of 40 nas with peak |i cc | < 200 ma, t <400 ns; 3 v 2.7 C 3.15 active mode; current pulses of 20 nas with peak |i cc | < 100 ma, t <400 ns; 1.8 v 1.62 C 1.92 i ccrip v cc ripple f ripple = 20 khz C 200 mhz C C 350 mv i ccmax card supply output current static load current, v cc > 1.65 v C C 40 ma stat ic load current, vcc > 4.6 v or 2.7 v as selected C C 90 i ccf i cc fault current class a, b (5 v and 3 v) 100 C 180 ma class c (1.8 v) 60 C 130 v sr vcc slew rate, rise rate on activate c f = 1.0 f 0.06 0.1 5 0.25 v/s v sf vcc slew rate, fall rate on de - activate c f = 1.0 f on v cc 0.07 5 0.15 0.6 v/s v rdy v cc ready voltage, v cc rising (rdy = 1) 5 v operation 4.6 C C v 3 v operation 2.75 C C 1.8 v operation 1.65 C C c f external filter capacitor (v cc to gnd) c f should be ceramic with low esr (< 100 m ) iso 7816 - 13 application 1.0 f emv 4.1 application 3.3 downloaded from: http:///
73S8009R data sheet ds_8009r_056 10 rev. 1.3 symbol parameter condition min nom max unit interface requirements C data signals: i/o, aux1, aux2, and host interfaces : i/ouc, aux1uc, aux2uc. i shortl , i shorth , and v inact requi rements do not pertain to i/ouc, aux1uc, aux2uc . v oh output level, high (i/o, aux1, aux2) i oh = 0 a 0.9 * v cc C v cc +0.1 v i oh = - 40 a 0.75 * v cc C v cc +0.1 v oh output level, high (i/ouc, aux1uc, aux2uc) i oh = 0 a 0.9 * v dd C v dd +0.1 v i oh = - 40 a 0.75 * v dd C v dd +0.1 v ol output level, low (i/o, aux1, aux2) i ol = 1 ma C C 0. 15 * v cc v v ol output level, low (i/ouc, aux1uc, aux2uc) i ol = 1 ma C C 0.3 v v ih input level, high (i/o, aux1, aux2) C 0.6 * v cc C v cc +0.30 v v ih input level, high (i/ou c, aux1uc, aux2uc) C 1.8 C v dd +0.30 v v il input level, low (i/o, aux1, aux2) C - 0. 15 C 0. 2 * v cc v v il input level, low (i/ouc, aux1uc, aux2uc) C - 0.3 C 0.8 v v in act output voltage when outside of session i ol = 0 C C 0.1 v i ol = 1 ma C C 0.3 i leak input leakage v ih = v cc C C 10 a i il input current, low (i/o, aux1, aux2) v il = 0 C C 0.65 ma i il input current, low (i/ouc, aux1uc, aux2uc) v il = 0 C C 0.7 ma i shortl short circuit output current for output low, shorted to v cc through 33 ? C C 15 ma i shorth short circuit output current for output high, shorted to ground through 33 ? C C 15 ma t r , t f output rise time, fall time for i/o, aux1, aux2, c l = 80 pf, 10% to 90%. for i/ouc, aux1uc, aux2uc, c l =50 pf, 10% to 90%. C C 100 ns t ir , t if input rise, fall times C C 1 s r pu internal pull - up resistor output stable for >200 ns 8 11 14 k ? fd max maximum data rate C C 1 mhz t fd io delay, i/o to i/ouc, aux1 to aux1uc, aux2 to aux2uc, i/ouc to i/o, aux1uc to aux1, aux2uc to aux2 (respecti vely falling edge to falling edge and rising edge to rising edge) e dge from master to slave measured at 50% point 60 100 200 ns t rd io C 25 90 c in input capacitance C C 10 pf downloaded from: http:///
ds_8009r_056 73S8009R data sheet rev. 1.3 11 symbol parameter condition min nom max unit reset and clock for card inte rface, rst, clk v oh output level, high i oh = - 200 a 0.9 * v cc C v cc v v ol output level, low i ol = 200 a 0 C 0.15*v cc v v in act output voltage when outside of session i ol = 0 C C 0.1 v i ol = 1 ma C C 0.3 v i rst_lim output current limit, rst C C C 30 ma i clk_lim output current limit, clk C C C 70 ma clk sr3v clk slew rate v cc = 3 v 0.3 C C v/ns clk sr5v clk slew rate v cc = 5 v 0.5 C C v/ns t r , t f output rise time, fall time c l = 35 pf for clk, 10% to 90% C C 8 ns c l = 200 pf for rst, 10% to 9 0% C C 100 duty cycle for clk c l =35 pf, f clk 20 mhz 45 C 55 % 2.4 digital signals characteristics table 5 lists the 73S8009R digital signals characteristics. table 5 : digital signals characteristics symbol parameter condition min nom max unit d ig it a l i / o e x c e p t f o r o s c i/o v il input l ow v oltage C - 0.3 C 0.8 v v ih input h igh v oltage C 1.8 C v dd + 0.3 v v ol output l ow v oltage i ol = 2 ma C C 0.45 v v oh output h igh v oltage i oh = -1 ma v dd - 0.45 C C v r out pull - up resistor; off , rdy C C 20 C k ? |i il1 | input l eakage c urrent gnd < v in < v dd C 5 a 2.5 dc characteristics table 6 lists the dc characteristics. table 6 : dc characteristics symbol parameter condition min nom max unit i dd supply current normal operation C 700 1500 a power down C C 5 i pc supply current v cc on, i cc = 0 , i/o, aux1, aux2 = high, clk not toggling C 450 650 a power down C C 5 i pcoff v pc supply current when v cc = 0 cmdvcc is high C 345 550 a downloaded from: http:///
73S8009R data sheet ds_8009r_056 12 rev. 1.3 2.6 voltage / temperature fault detection circuits table 7 lists the voltage / temperature fault detection circuits. table 7 : voltage / temperature fault detection circuits symbol parameter con dition min typical max unit v pcf v pc fault (v pc voltage supervisor threshold) v pc < v cc , a transient event C v cc > v pc + 0.3 C v v ccf rdy = 0 (v cc fault, v cc voltage supervisor threshold) v cc = 5 v C C 4.6 v v cc = 3 v C C 2.7 v cc = 1.8 v C C 1.65 t f die over temperature fault C 115 C 145 c i ccf card over current fault C 110 C 150 ma downloaded from: http:///
ds_8009r_056 73S8009R data sheet rev. 1.3 13 3 applications information this section provides general usage information for the design and implementation of the 73S8009R . 3.1 example 73S8009R schematics figure 4 shows a typical application schematic for the implementation of the 73S8009R . note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact teridian for the latest infor mation . so 28 clkin _ from _ uc c1 iso 7816 =1 f , emv =3.3 f pwrdn _ from _ uc off _ interrupt _ to _ uc clk track should be routed far from rst , i/o , c 4 and c 8 notes : 1 ) vdd = 2.7 v to 3.6 v dc . 2 ) vpc = 4. 75 v to 6.0 v dc ( class a -b- c reader : 1.8v , 3 v and 5 v cards ) 3 ) must be tied to gnd if not used 4 ) internal pull - up allows it to be left open if unused . i/ ouc _ to / from _ uc card detection switch is normally closed vdd aux 1 uc _ to / from _ uc aux 2 uc _ to / from _ uc see note 3 rstin _ from _ uc low esr (< 100mohms ) c1 should be placed near the sc connecter contact cs _ from _ uc cmdvcc 5_ from _ uc 73 s 80009 r 12 34 5 6 7 12 89 10 11 13 14 cs test 1 gnd vpc clkin aux 2 rdy pres pres i/o aux 1 n/c clk rst vcc test 2 cmdvcc 5 rstin vdd gnd off aux 2 uc aux 1 uc pwrdn i/ ouc r 2 20 k smart card connector 1 2 3 4 5 6 7 8 9 10 vcc rst clk c4 gnd vpp i/o c8 sw-1 sw-2 see note 4 cmdvcc 3 n/c n/c cmdvcc 3_ from _ uc rdy _ status _ to _ uc see note 1 c6 100nf vdd vpc c4 100nf c5 10uf see note 2 vdd 15 16 17 18 19 20 21 23 2827 25 24 2622 figure 4 : typical 73S8009R application schematic downloaded from: http:///
73S8009R data sheet ds_8009r_056 14 rev. 1.3 3.2 system controller interface four separate digital inputs allow direct control of the card interface from the host as foll ows: ? pin cs: enables the system controller interface. ? pin cmdvcc# and/or cmdvcc% : when low, starts an activation sequence. ? pin rstin: controls the card reset signal (when enabled by the sequencer). other functions are controlled as follows: ? pwrdn places the 73S8009R in a low power mode and shuts down all functions. ? the card clock is completely controlled by clkin. ? vcc output voltage valid is indicated on the rdy pin. ? interrupt output to the host: as long as the card is not activated, the off pin informs the host about the card presence only (low = no card in the reader). when cmdvcc is set low (card activation sequence requested from the host), a low level on off means a fault has been detected (e.g. card removal during card session, or voltage fault, or ther mal / over - current fault). this condition automatically initiates a deactivation sequence. 3.3 power supply and voltage supervision the teridian 73S8009R smart card interface ic incorporates a ldo voltage regulator. the voltage output is controlled b y the digital input sequence on cmdvcc# and cmdvcc% . this regulator is able to provide either 1.8 v, 3 v or 5 v card voltage s from the power supply applied on the vpc pin. digital circuitry is powered by the power supply applied on the vdd pin. v dd als o defines the voltage range to interface with the system controller. three voltage supervisors constantly check the presence of the voltages v dd , v pc and v cc . a card deactivation sequence is forced upon a fault detected by any of these voltage supervisor s. the voltage regulator can provide a card current of 65 ma in compliance with emv 4.1, and of at least 90 ma in compliance with iso7816 - 3. the v cc voltage supervisor threshold values are defined from the emv standard. 3.4 card power supply the card po wer supply is internally provided by the ldo regulator . the signals cmdvcc# and cmdvcc% control the turn - on, output voltage value, and turn - off of v cc . when either signal is asserted low, v cc will ramp to the selected value or if both signals are asserte d low (within 400 ns of each other), v cc will ramp to 1.8 volts. these signals are edge triggered. if cmdvcc% is asserted low (to command v cc to be 5 v ) and at a much later time (greater than 2 s, typically), cmdvcc# is asserted low, it will be ignored (and vice versa ). at the assertion (low) of either or both cmdvcc#/cmdvcc% signals , v cc will rise to the requested value. when v cc rises to an acceptable value, and stays above that value for approximately 20 s, rdy will be set high. approximately 510 s after the fall of cmdvcc#/cmdvcc% the circuit will check the see if v cc is at or above the required minimum value (indicated by rdy=1) and if not, will begin an emergency deactivation sequence. during the 510 s time, over - temperature, card removal, or de - assertion of cmdvcc#/cmdvcc% shall also initiate an emergency deactivation sequence. downloaded from: http:///
ds_8009r_056 73S8009R data sheet rev. 1.3 15 choice of the v cc capacitor: depending on the application, the requirements in terms of both the v cc minimum voltage and the transient currents that the interface must be able to provide to the card are different . an external capacitor must be connected between the vcc pin and the card ground in order to guarantee stabil ity of the ldo regulator, and to handle the transient requirements. the type and value of this capacitor can be optimized to meet the desired specification. table 8 shows the recommended capacitors for each v pc power supply configuration and applicable specification. table 8 : choice of vcc pin capacitor 3.5 over - temperature monitor a built - in detector monitors die temperature. when an over - temperature condition occurs, a card deactivation sequence is initiated, and an error or fault condition is r eported to the system controller via the off interrupt . 3.6 activation and deactivation sequence the host controller is fully responsible for the activation sequencing of the smart card signals clk, rst, i/o, aux1 and aux2. all of these signals are held low when the card is in the de activated state. upon card activation (the fall of cmdvcc#/cmdvcc% , all the signals will remain low until rdy goes high. the host should set the signals rstin, i/ouc, clkin, aux1uc and aux2uc low prior to a ctivating the card and allow rdy to go high before transitioning any of these signals. in order to initiate activa tion, the card must be present and there can be no over - temperature fault and no v dd fault. cmdvcc 3 or cmdvcc 5 vcc iouc io rdy rstin rst clkin clk ignored ignored ignored io, aux 1 , aux 2 , clk , rst are held low until rdy = 1 and cmdvccx = 0 io = iouc if rdy =1 clk = clkin if rdy =1 rst = rstin if rdy =1 t1 at t 1 ( 500 s) , if rdy = 0 or overcurrent , circuit will de - activate ( safety feature ) vcc valid figure 5 : acti vation sequence specification requirements system requirements specification min v cc voltage allowed during transient current max transient current charge min v pc power supply required capacitor type capacitor value emv 4. 1 4.6 v 30 na ? s 4.75 v x5r/x7 r with esr<100 m 3.3 f iso - 7816 -3 & gsm11.11 4.5 v 20 na ? s 4.75 v 1 f downloaded from: http:///
73S8009R data sheet ds_8009r_056 16 rev. 1.3 deactivation is initiated either by the system controller setting cmdvcc#/ cmdvcc% high, or automatically in the event of hardware faults. hardware faults are over - current, over - temperature and card extraction during the session. the host can manage the i/o signals, clkin, rstin, and cmdvcc#/cmdvcc% to create other de - activation sequences for non - emergency situations. cm dv cc % or cm dv cc # vcc i/ ouc i/o off rstin rst clkin clk 1 - off falls due to card removal or fault 5 - v cc is lowered note: host should set strobe low when off goes low , otherwise clk may be truncated 4 - i/ o falls approx 2 s after clk falls ~ 100 s 2 - rst forced low approx . 0. 6 s after off falls 3 - clk forced low approx . 7. 5 s after rst falls figure 6 : deactivation sequence 3.7 of f and fault detection the syste m controller can monitor the off signal to : ? q uery regarding the card presence outside of a card session ? detect fault s during card sessions. outside a card s ession in this condition, cmdvcc#/cmdvcc % ) is always high, off is low if the card is not present and high if the card is present. because it is outside a card session, any fault detection will not act upon the off signal. no deactivation is required during this time. during a ca rd session in this condition, cmdvcc#/cmdvcc % is always low and off fa lls low if the card is extracted or if any fault is detected. at the same time that off is set low, the sequencer automatically starts the deactivation process and the host should stop all transition on the signal lines. figure 7 shows the timing diagram for the signals cmdvcc #, cmdvcc % , pres and off during a card sessi on and outside the card session. downloaded from: http:///
ds_8009r_056 73S8009R data sheet rev. 1.3 17 pres off cmdvcc vcc outside card session within card session off is low by card extracted off is low by any fault within card session figure 7 : off activity outside and inside a card se ssion 3.8 power -d own operation a power - down function is provided that disables all analog functions. the power - down state is only allowed in the de - activated condition. the host invokes the p ower - down state when it is desirable to save power. the signals pres and pres are functional in the power - down state so that a card insertion asserts off high. i f there is no card present ( off = low) in power - down mode , the pull - up resistor is disabled so that no current is drawn from vdd. if a card is inserted, the pull - up resistor is enabled and off goes high. upon receiving the off indication, the host must then de - assert power down (pwrdn) and wait until the circuit is ready. when pwrdn is de - asserted, off goes low to indicate that the circuit is not ready (it is going through the power - on recovery time). when the circuit is ready, off will go high if the card is present. figure 8 illustrates the behavior of the circuit for pwrdn events . pres off pwrdn rc osc cmdvcc 3 / cmdvcc 5 rdy - indicates vcc is ok pwrdn while cmdvccx = 0 has no effect controller must wait for off = 1 after setting pwrdn = 0 before setting cmdvcc (3/5 )= 0 ~ 30 s pwrdn will have effect when cmdvccx =1 ~ 30 s off going high indicates circuit is ready off will go high if card is present and there are no faults off goes low when pwrdn is de - asserted while circuit starts up figure 8 : power - down operation downloaded from: http:///
73S8009R data sheet ds_8009r_056 18 rev. 1.3 3.9 chip select the cs pin is provided to allow multiple circuits to operate in parallel, driven f rom the same host control bus. when cs is high, the pins rstin, cmdvcc% , cmdvcc# and clkin control the chip as described. the pins iouc, aux1uc, and aux2uc operate to transfer data to the smart card via io , aux1, and aux2 when the smart card is activated. io, aux1, and aux2 have 11 k ? pull - up resistors while off and rdy have 20 k ? pull - up resistors. whe n cs goes low, the states of the pins rstin, cmdvcc% , cmdvcc# , and clkin are latched and held internally. the pull - up for pins iouc, aux1uc, and aux2uc become a very weak pull - up of approximately 3 microamperes. no transfer of data is possible between io uc, aux1uc, aux2uc and the smart - card signals io, aux1, and aux2. the signals off and rdy are set to high impedance and the internal 20 k ? pull - up resistors are disconnected. pwrdn is not latched when cs is low. the operation of the fault sensing circuits and card sense inputs (in regards to de - activation) are not affected by cs. cs off , i/ ouc , aux 1 uc , aux 2 uc control signals functional hi - z state hi - z state t sl t dz t is t si t id t di figure 9 : cs timing definitions 3.10 i/o circuitry and timing the states of the i/o, aux1, and aux2 pins are low after power - on - reset and they are high when the activation sequencer enables the i/o reception state. see section 3.6 activation and deactivation sequence for more details on when the i/o reception is enabled. the states of the i/ouc, aux1uc, and aux2uc are high after power on reset. within a card session and when the i/o reception state is turn ed on, the first i/o line on which a falling edge is detected becomes the input i/o line and the other becomes the output i/o line. when the input i/o line rising edge is detected , both i/o lines return to their neutral state. figure 10 shows the state diagram of how the i/o and i/ouc lines are managed to become input or output. the delay between the i/o signals is shown in figure 11 . downloaded from: http:///
ds_8009r_056 73S8009R data sheet rev. 1.3 19 neutral state i/ouc in i/o reception i/oicc in no yes no no no yes no yes i/o & not i/ouc i/ouc & not i/o i/ouc i/o yes yes figure 10 : i/o and i/ouc state diagram i/o i/ouc t i/o_hl t i/o_lh t i/ouc_hl t i/ouc_lh delay from i/o to i/ouc: t i/o_hl = 100 ns t i/o_lh = 15 ns delay from i/ouc to i/o: t i/ouc_hl = 100 ns t i/ouc_lh = 15 ns figure 11 : i/o to i/ouc delay timing diagram downloaded from: http:///
73S8009R data sheet ds_8009r_056 20 rev. 1.3 4 mechanical drawing s 4.1 20 - pin qfn figure 12 : 20 - pin qfn package dimensions 20 1 2 4.0 4.0 2.0 2.0 top view top view 1. 875 3. 75 2. 00 4. 00 1. 875 2. 00 3. 75 4. 00 2 3 1 0. 85 nom / 0. 90 max 0. 02 nom / 0. 05 max 0. 20 ref seating plane side view id 20 k 19 20 2 1 0. 50 0. 18 / 0. 30 0. 45 2. 50 / 2. 70 1. 25 / 1. 35 2. 50 / 2. 70 1. 25 / 1. 35 0. 20 min 0. 20 min 0. 30 bottom view downloaded from: http:///
ds_8009r_056 73S8009R data sheet rev. 1.3 21 4.2 28- pin so figure 13 : 2 8- pin so package dimensions .335 (8.509) .320 (8.128) .420 (10.668) .390 (9.906) .050 typ. (1.270) .305 (7.747) .285 (7.239) .715 (18.161) .695 (17.653) .0115 (0.29) .003 (0.076) .016 nom (0.40) .110 (2.790) .092 (2.336) pin no. 1 bevel downloaded from: http:///
73S8009R data sheet ds_8009r_056 22 rev. 1.3 5 ordering information table 9 lists the order numbers and packaging marks used to identify 73S8009R products. table 9 : order numbers and packaging marks p art description order number packaging mark 73S8009R C sol, 28 - pin l ead -f ree so 73S8009R - il/f 73S8009R - il 73S8009R C sol, 28 - pin lead - free so tape / reel 73S8009R - ilr/f 73S8009R - il 73S8009R C qfn, 20 - pin lead - free qfn 73S8009R - im/f 8009r 73S8009R C qfn, 20 - pin lead - free qfn tape / reel 73S8009R - imr/f 8009r 6 related documentation the following 73S8009R document s are available from teridian semiconductor corporation: 73S8009R 20qfn demo board user guide 73 s8009r 28so demo board user guide migrating from the 73s8024rn to the 73S8009R 7 contact information for more information about teridian semiconductor products or to check the availabili ty of the 73S8009R , contact us at: 6440 oak canyon road suite 100 irvine, ca 92618 - 5201 telephone: (714) 508 - 8800 fax: (714) 508 - 8878 email: scr.support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com . downloaded from: http:///
ds_8009r_056 73S8009R data sheet rev. 1.3 23 revision history revision date description 1.0 8/30/2005 first publication. 1. 2 12/11/2007 updated 28so package dimensions. removed leaded options. 1. 3 10/22 /200 9 formatted to the new teridian style. miscellaneous editorial changes. teridian semiconductor corporation is a registered trademark of teridian semiconduc tor corporation. simplifying system integration is a trademark of teridian semiconductor corpor ation. all other trademarks are the property of their respective owners. this data sheet is proprietary to teridian semiconductor corporation (t sc) and sets forth design goals for the described product. the data sheet is subject to change. tsc assumes no obligation r egarding future manufacture, unless agreed to in writing. if and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. ter idian semiconductor corporation (tsc) reserves the right to make changes in specifications at any time without noti ce. accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. tsc assumes no l iability for applications assistance. teridian semiconductor corp., 6440 oak canyon, suite 100, irvine, ca 9 2618 tel (714) 508 - 8800, fax (714) 508 - 8877, http://www.teridian.com downloaded from: http:///

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